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description the CXD2043Q is an adaptive comb filter compatible with ntsc system, and can provide high-precision y/c separation with a single-chip. features y/c separation by adaptive processing horizontal aperture compensation circuit 8-bit a/d converter (1-channel) 8-bit d/a converter (2-channel) two 1h delay lines 4-pll absolute maximum ratings (ta = 25?, vss = 0v) supply voltage dv dd v ss ?0.5 to +7.0 v yv dd v ss ?0.5 to +7.0 v cv dd v ss ?0.5 to +7.0 v pv dd v ss ?0.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? block diagram recommended operating conditions supply voltage dv dd 5.0 0.25 v yv dd 5.0 0.25 v cv dd 5.0 0.25 v pv dd 5.0 0.25 v operating temperature topr ?0 to +75 ? structure silicon gate cmos ic applications y/c separation for color tvs and vcrs ?1 CXD2043Q e95812-st digital comb filter (ntsc) sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 80 pin qfp (plastic) 27 71 to 78 31 41 vi8 to vi1 adin a/d bpf bpf bpf 1hdl 1hdl dl dac dac adaptive filter operation logic operation vco phase comparison 1/4 4fsc c8 to c1 aco y8 to y1 ayo 43 to 48 51 52 54 to 61 9 10 12 vcv cpo fin
? 2 CXD2043Q pin configuration pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 oclk dv ss dv dd clko mck adck ck4 test fin cpo pv ss i o i i o i i o clock amplifier input. input at 0.8vp-p or more by eliminating dc components with a capacitor. digital ground digital power supply clock amplifier output. left open when the clock amplifier is not used. master clock input clock input for a/d converter. input the same clock signal as for pin 5. 4fsc clock output. generated from the built-in 4-pll. test. fix to low. fsc clock input. input fsc which is burst-locked. connect to dvss when the pll is not used. phase comparison output for the built-in pll. left open when the pll is not used. pll analog ground symbol i/o description 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 o c l k d v s s d v d d c l k o m c k a d c k c k 4 t e s t f i n c p o p v s s v c v t e s t t e s t v c e n t e s t p v d d c l p i c p o n a d v d a d v s i c p c r v g r t s t a p c n x c o e c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 x y o e y 1 y 2 d v d d d v s s y 3 y 4 y 5 y 6 y 7 y 8 c v s s a c o c v d d c v g c v r f c i r f v b y i r f y v r f y v g y v d d a y o y v s s r t a a v d a d i n a a v s r b d v s s d v d d t e s t t e s t t e s t b p f v i 8 v i 7 v i 6 v i 5 v i 4 v i 3 v i 2 v i 1 a d c o i n s l
? 3 CXD2043Q pin no. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 vcv test test vcen test pv dd clpi cpon advd advs icp crv gr rb aavs adin aavd rt yvss ayo yvdd yvg yvrf yirf vb cirf cvrf cvg cvdd aco cvss y8 y7 y6 i i i i o i i i i o i o o o i i o o i o o o o o control voltage input for the built-in vco oscillation. connect to pvss when the pll is not used. test. fix to low. test. fix to low. built-in vco oscillation enable. connect to pv dd when using the pll. connect to pvss when the pll is not used. test. left open. pll analog power supply clamp pulse input for a/d converter (negative polarity). connect to dv dd when the clamp is off. high: clamp function is set to off, and only the normal a/d converter function is enabled. low: clamp function is enabled. digital power supply for a/d converter digital ground for a/d converter clamp control voltage clamp reference voltage input connect to analog ground. a/d converter reference voltage (bottom) analog ground for a/d converter comb filter analog input (a/d converter input) analog power supply for a/d converter a/d converter reference voltage (top) analog ground for y-d/a converter analog luminance signal output analog power supply for y-d/a converter connect to yvdd via a capacitor of approximately 0.1 f. vrf for y. sets the output full-scale value for y. connect a resistor of 16 times (16r) that of the output resistor "r" of ayo pin. connect to yvss via a capacitor of approximately 0.1 f. connect a resistor of 16 times (16r) that of the output resistor "r" of aco pin. vrf for c. sets the output full-scale value for c. connect to cvdd via a capacitor of approximately 0.1 f. analog power supply for c-d/a converter analog chroma signal output analog ground for c-d/a converter digital luminance signal output (msb) digital luminance signal output digital luminance signal output symbol i/o description
? 4 CXD2043Q pin no. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 y5 y4 y3 dv ss dv dd y2 y1 xyoe c8 c7 c6 c5 c4 c3 c2 c1 xcoe apcn tst dv ss dv dd test test test bpf vi8 vi7 vi6 vi5 vi4 vi3 o o o o o i o o o o o o o o i i i i i i i i i i i i i digital luminance signal output digital luminance signal output digital luminance signal output digital ground digital power supply digital luminance signal output digital luminance signal output (lsb) digital luminance signal output control high: high impedance low: standard output digital chroma signal output (msb) digital chroma signal output digital chroma signal output digital chroma signal output digital chroma signal output digital chroma signal output digital chroma signal output digital chroma signal output (lsb) digital chroma signal output control. high: high impedance low: standard output aperture compensation switching. high: aperture compensation on low: aperture compensation off y output through mode. high: outputs the input composite video signal from the y output. at this time, there is 1h + 18 clock delay from the input. low: y/c separation mode digital ground digital power supply test. fix to low. test. fix to low. test. fix to low. high: fixed to bpf separation low: standard mode digital composite video input (msb) digital composite video input digital composite video input digital composite video input digital composite video input digital composite video input symbol i/o description
? 5 CXD2043Q pin no. 77 78 79 80 vi2 vi1 adco insl i i i i digital composite video input digital composite video input (lsb) high: video signals taken in form a/d converter are output from the y output pins (y8 to y1) as 8-bit digital data with a 3.5 clock delay. low: normal mode input switching. high: digital input low: analog input. symbol i/o description
? 6 CXD2043Q electrical characteristics dc characteristics (v dd = 5 0.25v, v ss = 0v, ta = ?0 to +75 c) item symbol conditions min. typ. max. unit supply voltage 4.75 ?0 v dd 0.7 v ss v dd ?0.8 v ss 0.8 250k dv dd aavd advd yvdd cvdd topr i dd v ih v il v oh v ol lvth v in r fb ac characteristics (v dd = 5 0.25v, v ss = 0v, ta = ?0 to +75 c, c l = 20pf) item symbol conditions min. typ. max. unit t dsu t dh t pd f mck ? vi [8 : 1] mck ? vi [8 : 1] mck ? y [a : 1] mck ? c [a : 1] 15.0 10.0 14 4fsc 40 15 ns ns ns mhz data setup time data hold time propagation delay time clock frequency pin capacitance (ta = 25 c, f = 1mhz, v in = v out = 0v) item symbol conditions min. typ. max. unit c in c out 9 11 pf pf input capacitance output capacitance 5.0 v dd /2 1m 5.25 +75 80 v dd v dd 0.3 v dd 0.4 v dd 2.5m v c ma v v v v vp-p operating temperature supply current high level input voltage low level input voltage high level output voltage low level output voltage logical vth input voltage feedback resistor clock 14mhz cmos level cmos level i oh = ?ma i oh = ?ma (pins 4, 7) i ol = 4ma i ol = 8ma (pins 4, 7) oclk (pin 1)
? 7 CXD2043Q adc characteristics (v dd = 5v, ta = 25 c, f = 10mhz) item symbol conditions min. typ. max. unit resolution max. conversion speed analog input band width self bias propagation delay time differential linearity error integral linearity error clamp offset voltage n fmax bw vrb vrt ?vrb t pd e d e l e oc ?db v ref = vrb v ref = vrt 14.3 0.48 1.96 ?.0 ?.0 ?0 ?0 8 18 0.52 2.08 0 ?0 0.56 2.22 45 +1.0 +3.0 +20 +10 bit msps mhz v v ns lsb lsb mv mv dac characteristics (v dd = 5v, v rf = 2v, i rf = 3.3k , r = 200 , ta = 25 c, f = 10mhz) item symbol conditions min. typ. max. unit resolution max. conversion speed differential linearity error integral linearity error output full-scale voltage output full-scale current output offset voltage precision guaranteed output voltage range glitch energy n fmax e d e l v fs i fs v os v oc g e * 1 14.3 ?.5 ?.5 1.805 1.8 8 1.90 9.5 30 +0.5 +1.5 1.995 15 1.0 2.1 bit msps lsb lsb v ma mv v pv-s * 1 r = 75 , 1vp-p output
? 8 CXD2043Q application circuit for a/d converter (1) in the case of input clamp pulse directly. 0 . 0 1 7 5 1 0 p 4 7 a d c i n p u t 0 . 0 1 2 0 k 0 . 0 1 0 . 1 0 . 1 c l a m p p u l s e a d c c l o c k r t a d i n r b c r v i c p g r a a v d a a v s c l p i c p o n a d c k a d v d a d v s 2 9 2 7 2 5 2 3 2 2 2 4 2 8 2 6 1 8 1 9 6 2 0 2 1 (2) in the case of not using the internal clamp circuit 0 . 0 1 7 5 1 0 p a d c i n p u t 0 . 0 1 0 . 1 0 . 1 a d c c l o c k r t a d i n r b c r v i c p g r a a v d a a v s c l p i c p o n a d c k a d v d a d v s 2 9 2 7 2 5 2 3 2 2 2 4 2 8 2 6 1 8 1 9 6 2 0 2 1
? 9 CXD2043Q application circuit for d/a converter 0 . 1 0 . 1 c l o c k 2 0 0 ( r ) y o u t p u t 1 k 0 . 1 3 . 3 k ( r ' ) 0 . 1 2 0 0 ( r ) c o u t p u t 1 k 0 . 1 3 . 3 k ( r ' ) y v d d y v s s m c k d v d d d v s s c v d d c v s s a y o y v g y v r f y i r f v b a c o c v g c v r f c i r f 3 2 3 0 5 4 0 4 2 3 1 3 3 3 4 3 5 3 6 4 1 3 9 3 8 3 7 method of selecting output resistance the CXD2043Q has a built-in current output-type d/a converter. to obtain the output voltages, connect resistances to ayo and aco pins. the voltage and current specifications are: output full-scale voltage: v fs = 0.5 to 2.0v output full-scale current: i fs = 0 to 15ma calculate the output resistance using the relationship v fs = i fs r. in addition, connect a resistance of 16 times the output resistance to the reference current pin (yirf, cirf). in the case where the value comes to be impractical, use a value of resistance as close to the value calculated as possible. note that, at this time, v fs = v rf 16r/r' (v rf : pin voltage of yvrf and cvrf). r is the resistance connected to ayo/aco, and r' is the resistance connected to yirf/cirf. power consumption can be reduced by using higher resistance values, but then glitch energy and data settling time increase contrastingly. select optimum resistance values according to the system applications. v dd , v ss separate the analog and digital systems around the device to reduce noise effect. yv dd and cv dd are respectively by-passed to yv ss and cv ss as close to each other as possible through ceramic capacitor of approximately 0.1 f.
? 10 CXD2043Q application circuit i n o u t g n d 1 2 3 a 5 v y o u t i n o u t g n d 2 1 3 a 5 v v i d e o i n i n o u t g n d 1 2 3 a 5 v c o u t a 5 v a 5 v 0 . 0 1 0 . 1 3 . 3 k 0 . 1 3 . 3 k 0 . 1 a 5 v 2 2 0 0 . 0 1 0 . 1 0 . 1 0 . 1 0 . 1 c v r f 1 0 k y v v r f 1 0 k 0 . 0 1 2 2 0 d 5 v d 5 v 0 . 0 1 0 . 0 0 1 f s c i n d 5 v 0 . 0 1 d 5 v v r e f 5 k 1 0 0 . 0 1 0 . 0 1 5 6 k 5 6 0 k 0 . 0 2 2 a 5 v 7 0 6 9 6 8 6 7 6 5 6 6 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 d v s s d v d d t e s t t e s t t e s t b p f v i 8 v i 7 v i 6 v i 5 v i 4 v i 3 v i 2 v i 1 a d c o i n s l 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 c v d d c v g c v r f c i r f v b y i r f y v r f y v g y v d d a y o y v s s r t a a v d a d i n a a v s r b 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 t s t a p c n x c o e c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 x y o e y 1 y 2 d v d d d v s s y 3 y 4 y 5 y 6 y 7 y 8 c v s s a c o 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 1 o c l k d v s s d v d d c l k o m c k a d c k c k 4 t e s t f i n c p o p v s s v c v t e s t t e s t v c e n t e s t p v d d c l p i c p o n a d v d a d v s i c p c r v g r c x d 2 0 4 3 q c l a m p p u l s e i n i c 1 4 7 l p f l p f l p f n p n application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 11 CXD2043Q package outline unit: mm p a c k a g e s t r u c t u r e s o n y c o d e e i a j c o d e j e d e c c o d e q f p - 8 0 p - l 0 1 q f p 0 8 0 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 1 . 6 g 2 3 . 9 0 . 4 2 0 . 0 0 . 1 + 0 . 4 1 8 0 6 5 6 4 4 1 4 0 2 5 2 4 0 . 8 0 . 3 5 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 + 0 . 4 1 7 . 9 0 . 4 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 2 . 7 5 0 . 1 5 + 0 . 3 5 0 . 8 0 . 2 0 . 1 5 0 . 0 5 + 0 . 1 8 0 p i n q f p ( p l a s t i c ) m 0 . 2 0 . 1 5 0 t o 1 0 d e t a i l a a

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